The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, device driving current improvement becomes more important. Device current is closely related to gate length, gate capacitance, and carrier mobility. Shortening poly-gate length, increasing gate capacitance, and increasing carrier mobility can improve the device's current performance. Gate length reduction is an on-going effort in order to shrink circuit size. Increasing gate capacitance has also been achieved by efforts such as reducing gate dielectric thickness, increasing gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored.
Among efforts made to enhance carrier mobility, forming a strained silicon channel is a known practice. Strain, some times referred to as stress, can enhance bulk electron and hole mobility. The performance of a MOS device can be enhanced through a strained-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
When silicon is placed under strain, the in-plane, room temperature electron mobility is dramatically increased. One way to develop strain is by using a graded SiGe epitaxy layer as a substrate on which a layer of relaxed SiGe is formed. A layer of silicon is formed on the relaxed SiGe layer. MOS devices are then formed on the silicon layer, which has inherent strain. Since the lattice constant of SiGe is larger than that of Si, the Si film is under biaxial tension and thus the carriers exhibit strain-enhanced mobility.
Strain in a device may have components in three directions; parallel to the MOS device channel length, parallel to the device channel width, and perpendicular to the channel plane. The strains parallel to the device channel length and width are called in-plane strains. Research has revealed that bi-axial, in-plane tensile strain field can improve nMOS performance, and compressive strain parallel to channel length direction can improve pMOS device performance.
Strain can also be applied by forming a strained contact etching stop (CES) layer on MOS device. When a contact etching stop layer is deposited, due to the lattice spacing mismatch between the CES layer and underlying layer, an in-plane stress develops to match the lattice spacing. FIG. 1 illustrates a conventional nMOS device having a strained channel region. CES layer 14 has inherent tensile strain. The portions 14a of the CES layer on the top of the source/drain regions 12 introduce a compressive strain in source/drain regions 12 and thus cause a tensile strain in channel region 11. Therefore, the carrier mobility in the channel region 11 is improved. However, the CES layer 14 is uni-strained, which means that the same tensile strained CES layer is also capped on the top of the gate electrode 6 and spacers 8. The cap portion has the effect of introducing compressive strain into the underlying regions including channel region 11 so that the overall channel tensile strain is reduced.
The strain in the channel region 11 can be improved by forming an uncapped CES layer, in which the CES layer 14 is not formed on top of the electrode 6 and spacers 8. What is needed, however, is a method of improving a CES layer's ability to impose desirable strain to the channel without adding much complexity into the manufacturing process.